FPGA Design Engineer
We are seeking experienced FPGA Engineers with 3–20 years of industry experience for our client projects.
Responsibilities:
• Own RTL design from specification → micro-architecture → implementation
• Develop synthesizable Verilog/SystemVerilog RTL for performance-critical blocks
• Integrate and configure FPGA IPs
• Perform synthesis, place-and-route, static timing analysis, and timing closure
• Debug functional and timing issues using simulation, waveforms, and on-chip debug tools
• Run Lint, CDC/RDC, and basic formal checks to ensure design quality
• Support FPGA prototyping, board bring-up, and lab debugging
• Collaborate closely with verification, board, and embedded teams
• Prepare design documentation and participate in code reviews
Must-Have Skills:
• Strong Verilog/SystemVerilog and digital design fundamentals
• Experience with FPGA toolchains: Xilinx Vivado, Intel Quartus, or Lattice Diamond
• Solid understanding of FSMs, pipelining, CDC, reset strategies, and clocking
• Proficiency in simulation and debug tools: Questa, ModelSim, or VCS
Nice-to-Have Skills:
• Experience with scripting (TCL, Python) for build and flow automation
• Familiarity with FPGA-to-ASIC prototyping flows
• Experience with lab instruments (ILA, logic analyzer, oscilloscope)
• Exposure to UVM or self-checking testbenches
How to Apply:
Submit your resume via the Submit Application Form below.
ASIC RTL Engineer
We are looking for ASIC RTL Engineers with 3–20 years of experience to support our client engagements.
Responsibilities:
• Own RTL design from specification → micro-architecture → implementation for ASIC designs
• Develop synthesizable Verilog/SystemVerilog RTL for performance-critical IP and SoC blocks
• Implement and integrate standard interfaces such as AXI/APB, DDR, PCIe, Ethernet, or custom protocols
• Perform RTL linting, CDC/RDC analysis, and basic formal checks
• Collaborate closely with verification teams for functional correctness and coverage closure
• Support synthesis readiness and work with physical design teams on timing and QoR targets
• Debug functional issues using simulation and waveform analysis
• Participate in design reviews and ensure adherence to coding and design guidelines
• Prepare detailed design documentation and specifications
Must-Have Skills:
• Strong Verilog/SystemVerilog and digital design fundamentals
• Solid understanding of ASIC RTL design methodologies and flows
• Experience with clocking, resets, FSMs, pipelining, and low-power design concepts
• Familiarity with lint, CDC, and static analysis tools
• Proficiency with simulation tools such as Questa, VCS, or Xcelium
Nice-to-Have Skills:
• Experience with low-power design (UPF/CPF)
• Exposure to SoC integration and top-level RTL
• Familiarity with high-speed protocols (DDR, PCIe, Ethernet)
• Experience working with synthesis and STA tools
• Exposure to scripting (TCL, Python) for flow automation
How to Apply:
Submit your resume via the Submit Application Form below.
ASIC Verification Engineer
We are looking for ASIC Verification Engineers with 3–20 years of experience to support our client engagements.
Responsibilities:
• Develop and maintain SystemVerilog/UVM-based verification environments for ASIC and SoC designs
• Create reusable verification components including sequences, drivers, monitors, scoreboards, and coverage models
• Develop constrained-random and directed test cases to validate functional correctness
• Perform functional, code, and assertion coverage analysis and drive coverage closure
• Debug RTL and testbench issues using waveform analysis and simulation logs
• Collaborate closely with RTL design and architecture teams to define verification strategies
• Execute regression tests and ensure verification stability and quality
• Write and maintain SystemVerilog assertions (SVA) for protocol and design checks
• Participate in design and verification reviews and document verification results
Must-Have Skills:
• Strong hands-on experience with SystemVerilog and UVM methodology
• Solid understanding of ASIC/SoC verification flows and methodologies
• Experience with verification of standard protocols such as AXI, APB, AHB, or similar interfaces
• Proficiency with simulators such as Questa, VCS, or Xcelium
• Strong debugging skills using waveforms, logs, and assertions
Nice-to-Have Skills:
• Experience with formal verification tools and methodologies
• Exposure to verification of high-speed interfaces (DDR, PCIe, Ethernet)
• Familiarity with scripting (Python, Perl, TCL) for regression and automation
• Exposure to FPGA prototyping or emulation-based verification
• Experience with low-power verification using UPF/CPF
How to Apply:
Submit your resume via the Submit Application Form below.
ASIC Layout Engineers
We are looking for Experience Layout Engineers to support our clients engagements.
Responsibilities:
• Perform full-custom and semi-custom layout for analog, digital, and mixed-signal ASIC blocks
• Execute layout for critical circuits such as amplifiers, comparators, ADC/DAC blocks, PLL components, bandgaps, LDOs, SRAMs, and standard cells
• Ensure adherence to layout best practices including matching, symmetry, shielding, and device optimization
• Perform DRC, LVS, and PEX checks and resolve layout-related issues efficiently
• Optimize layouts for performance, area, power, signal integrity, and manufacturability
• Collaborate closely with circuit designers to understand design intent and layout sensitivities
• Handle floorplanning, guard rings, isolation, and analog–digital boundary layouts
• Support EM/IR, reliability, and layout-dependent effect (LDE) checks
• Participate in design reviews, sign-off activities, and GDSII tape-out
Must-Have Skills:
• Strong hands-on experience with Cadence Virtuoso Layout Suite (XL/GXL)
• Proficiency with DRC/LVS/PEX tools such as Calibre or Assura
• Solid understanding of analog layout techniques (common-centroid, interdigitation, matching)
• Experience with mixed-signal layout and floorplanning methodologies
• Familiarity with foundry PDKs, design rules, and DFM requirements
Nice-to-Have Skills:
• Experience with advanced technology nodes (28nm, 16nm, 7nm, FinFET)
• Exposure to EM/IR and reliability sign-off flows
• Scripting experience (SKILL, Python) for layout automation
• Experience with memory layout or standard-cell layout
• Knowledge of ESD, latch-up, and reliability guidelines
How to Apply:
Submit your resume via the Submit Application Form below.
Embedded Firmware Engineer
We are looking for Embedded Firmware Engineers to support our clients engagements.
Responsibilities:
• Design, develop, and maintain embedded firmware for SoC, FPGA-based, and microcontroller systems
• Develop low-level drivers for peripherals such as UART, I2C, SPI, PCIe, Ethernet, and GPIO
• Work on bare-metal and RTOS-based firmware development
• Support board bring-up, hardware-software integration, and system-level debugging
• Debug firmware issues using JTAG, logic analyzers, oscilloscopes, and software debuggers
• Collaborate closely with FPGA, hardware, and system teams for end-to-end integration
• Optimize firmware for performance, memory footprint, and power consumption
• Develop and maintain firmware documentation and coding guidelines
• Participate in code reviews and ensure firmware quality and reliability
Must-Have Skills:
• Strong proficiency in C/C++ for embedded systems
• Solid understanding of microcontroller and SoC architectures
• Experience with bare-metal and RTOS environments (FreeRTOS, Zephyr, etc.)
• Hands-on experience with peripheral driver development
• Familiarity with debugging tools such as JTAG, GDB, and vendor-specific debuggers
Nice-to-Have Skills:
• Experience with embedded Linux and device driver development
• Exposure to FPGA–processor interfaces (AXI, APB)
• Familiarity with scripting (Python, Shell) for automation and testing
• Experience with communication stacks and protocols
• Knowledge of secure boot, firmware update mechanisms, and safety standards
How to Apply:
Submit your resume via the Submit Application Form below.
PCB & Hardware Engineer
We are looking for PCB Engineers to support our client engagements.
Responsibilities:
• Design and develop multi-layer PCBs for digital, analog, RF, and mixed-signal systems
• Create schematics, PCB layouts, and libraries using tools such as Altium, Cadence Allegro/OrCAD, Mentor PADS, or KiCad
• Define PCB stack-ups, impedance requirements, and routing constraints for high-speed designs
• Perform placement and routing for interfaces such as DDR, PCIe, Ethernet, USB, LVDS, and SERDES
• Collaborate with FPGA, ASIC, power, and mechanical teams for board-level integration
• Conduct DFM/DFT reviews and work closely with fabrication and assembly vendors
• Generate fabrication and assembly deliverables including Gerber/ODB++, BOM, and drawings
• Support prototype bring-up, board debugging, and design re-spins
• Ensure designs meet signal integrity, power integrity, thermal, and EMI/EMC requirements
Must-Have Skills:
• Strong experience in multi-layer PCB design
• Proficiency with PCB design tools such as Altium, Allegro, PADS, or KiCad
• Solid understanding of high-speed routing, impedance control, and differential pairs
• Knowledge of power distribution, grounding, and decoupling techniques
• Familiarity with PCB fabrication and assembly processes
Nice-to-Have Skills:
• Experience with SI/PI analysis tools (HyperLynx, Sigrity, or similar)
• Exposure to FPGA/SoC-based board designs
• Knowledge of EMI/EMC standards and compliance practices
• Familiarity with scripting or automation for PCB workflows
• Experience supporting board bring-up and validation
How to Apply:
Submit your resume via the Submit Application Form below.
Hiring Temporarily on Hold
We are currently not accepting new job applications.
Hiring will resume once new requirements are finalized.
We appreciate your interest and encourage you to revisit this page for future opportunities.